This simple board was used for initial development of the eForth and polyFORTH virtual machines for the GA144 using Cypress SRAM.  It was intended solely for in-house development use, depending on an external regulated power supply and on external 1.8v serial interface for reset, programming, and development using the IDE.

To use the eForth terminal, one wire had to be added connecting J5 pin 5 with G144 pin 20 (100_17).

To protect the SRAM against writing during chip reset, we reworked the board by adding 1k pull-up resistors to 008_1 (CE-) and 008_3 (WE-).

After the SRAM control code was up and running we realized that the mapping of high order SRAM address lines was unfortunate, particularly address line 0 going to 008_5.  For a maximum size (1 Mword) SRAM this did not matter.  If this circuit were to be used with any of hte smaller versions of that same SRAM, the address line routing used on the Test Board (TB001) should be used instead.

Another thing absent from this board is a jumperable pull-up on 705_17 (The SO line from the SPI flash.)  That should be added if one intends to do much work with the flash.  The correct setting for J3 is 2-3 so that the flash sees the reset signal coming from IDE.

Finally, this board does not have a reset circuit.  The reset function is completely controlled by the IDE interface through J6 or J4.  For a standalone application booting from flash, an RC reset circuit would be needed.
